81348 Datasheet, PDF (72/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Electrical Specifications
4.3.3 Peripheral Bus Interface Signal Timings
Table 25. Peripheral Bus Interface Signal Timings
Symbol
Parameter
Min.
Nom.
Max. Units
A2D Address to Data wait-states
4
-
20 clks
D2D Data to Data wait-states
4
-
20 clks
REC Recovery wait-states
1
-
20 clks
N Number of Data phases
1
-
4 phases
Tasc Address setup to CE#
25
30
-
ns
Taso Address setup to OE#
10
15
-
ns
Tasw Address setup to WE#
25
30
-
ns
Tah Address hold from CE#,OE#
Nom - 5
REC × 15
-
ns
Tahw Address hold from WE#
Nom - 5
(REC+1) × 15
-
ns
Twce CE# pulse width
Nom - 5
1()A(D2D2D++22+))()(×N ^-15
-
ns
Twoe OE# pulse width
Nom - 5
1()A(D2D2D++32+))()(×N ^-15
-
ns
Twwe WE# pulse width
Nom - 5
(A2D + 1) × 15
-
ns
Tdsw Write Data setup to WE#
Nom - 5
(A2D + 1) × 15
-
ns
Tdhw Write Data hold from WE#
10
15
20
ns
Tad1 1st Read Data access time from Address
-
(A2D + 4) × 15
Nom -
11
ns
TadN Nth Read Data access time from Address
-
(D2D + 2) × 15
No1m1 - _ns
Tcd Read Data access time from CE#
-
(A2D + 2) × 15
No1m1 - _ns
Toe Read Data access time from OE#
0
(A2D + 3) × 15
Nom -
11
ns
Tdh Read Data hold time from Address, CE#, OE# 0
(REC + 2) × 15
Nom - 5 ns
N_1.otes: _{See Figure 25, “PBI Output Timings” on page 85 and Figure 26, “PBI External Device Timings (Flash)” on page 86.}
DInatteal^®sh8e1et348 ^{I/O Processor}
72
December 2007
Order Number: 315038-003US