81348 Datasheet, PDF (34/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Package Information
Table 13.
Reset Strap Signals (Sheet 2 of 3)
Name
Count Type
PCIE_RC#
1
RSetrsaept
SSSSMMMMBBBB____AAAA5321,,,
4
RSetrsaept
PCIX_PULLUP#
PCIX_32BIT#
PCIXM1_100#
HS_SM#
1
RSetrsaept
1
RSetrsaept
1
Reset
Strap
1
RSetrsaept
FW_TIMER_OFF#
1
RSetrsaept
CONTROLLER_ONLY#
1
RSetrsaept
LK_DN_RST_BYPASS#
1
RSetrsaept
Description
PinCtIe-rEfaRceoootpCeoramtepsleaxs: Daneteenrmdpinoienst worheathroeortPcCoImEpxlperxe.ss*
0 = Root complex
1_No=_teE_:ndMpouixnetd(doenftaoulstigmnoadl e_A)_[12]
uSnesttuinpgpobrotethd.^{PCIX_EP# and PCIE_RC# to endpoint is}
SbreiMts[p1Bo]unwsdhsAedtroderwebshitses:n[M7a:ac0pc]serstesopirasedasdetrtneetsmsapdbtdietrd[e5.s]s, _SbMit[B3u]s, bsliat[v2e],paorntd
0 = Address bit is low
NNN^1Noooo=tttteeee^A::::^ddSSSS^reMMMM^ssBBBB____^biAAAA^t3215^{ismmmmhiuuuugxxxxheeeedddd(dooooennnnfattttooooulsssstiiiimggggnnnnoaaaadlllleAAAA)[[[[11116543]]]]}
PpreCuslIlo--XuurpPcseuellbnUuaspb:kleeDdee.ptTeehrrsme.sienemsawyhbeethuesrePdCfIoirnttheerfacceenthraals on-die
01_No==_teED_:nisaaMbbluelexPePCdCIIopnputuloll-l-usuipgpnrreaeslsi_Asist_[to1orr7ss_{](default mode)}
32-Bit PCI-X Bus: Indicates width of the PCI-X bus to PCI-X
Sinta3t2u-sbRitemgiosdteer.. Enables pull-ups for upper half of bus when
01_No==_te36_:24--bbMiittuxwweiidddeeoPPnCCtoII--sXXigbbnuuassl _{(Ad[e1fa8u]lt mode)}
PthCiIs-XbitMloimdeits1P1C0I0-XMbHuzsEtnoa1b0le0:MInHzCewnhtirlaeliRnemsooudrece1:Mode,
0 = Limit PCI-X mode 1 to 100 MHz
1_No=_te1_:33MMuHxezdenoanbtolesdig(ndaefla_Au_[lt₁m_9]ode)
Hot Swap Startup Mode: In End Point Mode, this bit
determines whether Hot Swap mode is enabled.
01_{No==teHH:oottMSSuwwxaaeppdMMooonddtoee sdeinigsanababllleeA}dd_{[(2d1e]fault mode)}
Fdiervmewloaprme _{eTnimt aenrdOdffe:bDuigs.aWblehsen40e0namblSedfi,rmtimwearreautitmomeraftoicrally}
c4bl0iet0afrumsnSCctoironenfgisgauradrsalentsioosrnmoCfayplcrbloeacseResedstoroyrns(stCatCateRte.) _{WobfihtCeiFnnGPd_CisCSaYRbCleLaEdft_,eECr NC#R}
pin at rising edge of P_RST#.
0 = Firmware timer disabled
1_No=_teF_:irmMwuaxreedtiomnetor esinganballe_Ad_[(₂d₂ef_]ault mode)
Controller-Only Enable:
01_No==_teCR_:oAnIDMtruoexlnleeadrboloenndltyo(,dRseiAgfaInDualltd_Amis[ao₂bd₃lee_])d
LwionukldDonwornmRaellsyetbeBycpaaussse:dDbiysaablLeisnkthDeofwulnl cohriphortesreestetth.at
01_No==_teDR_{:eosneMotutoxnreedLsieontnkotoDnosLwiignnnka(DldAeofw[a2}nu_4lt]mode)
DInatteal^®sh8e1et348 ^{I/O Processor}
34
December 2007
Order Number: 315038-003US