81348 Datasheet, PDF (15/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Package Information—Intel^® 81348
3.0
3.1
3.2
3.2.1
Table 1.
Package Information
Package Introduction
The 81348 is offered in a 1357-ball FCBGA5 package.
Functional Signal Definitions
This section defines the pins and signals.
Signal Pin Descriptions
Pin Description Nomenclature
Symbol
Description
I
O
I/O
OD
PWR
GND
—
Sync(...)
Async
R/W
Rst(P)
Rst(M)
Rst(PB)
Rst(T)
ActLow
Diff
Input pin only
Output pin only
Pin can be either an input or an output
Open-drain pin
Power pin
Ground pin
Pin must be connected as described
Synchronous. Signal meets timings relative to a clock.
• Sync(P): Synchronous to P_CLKIN
• Sync(M): Synchronous to M_CK[2:0] / M_CK#[2:0]
• Sync(T): Synchronous to TCK
Asynchronous. Inputs can be asynchronous relative to all clocks. All asynchronous signals
are level-sensitive.
Indicates read or write capability.
The pin is reset with WARM_RST# or P_RST#.
The pin is reset with M_RST#. M_RST# is asserted when the memory subsystem is reset.
TInhteerpfianceissruebsseytswteitmh P_isB_r__esR_eS_tT_. OUT#. PB_RSTOUT# is asserted when the Peripheral Bus
The pin is reset with TRST#.
The pin is an active-low signal.
The pin is a differential signal pair.
• “P” at the end of a differential pin name indicates “positive”.
• “N” at the end of a differential pin name indicates “negative”.
December 2007
Order Number: 315038-003US
Intel^® 81348 I/ODParotacsehsesoert
15