81348 Datasheet, PDF (14/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Features
2.2.11
2.2.12
2.2.13
2.2.14
2.2.15
Interrupt Controller Unit
Each Intel XScale^® processor supports an Interrupt Controller Unit (ICU). The ICU
aggregates interrupt sources both external and internal sources of the
81348 to the Intel XScale^® processor. The ICU supports high-performance interrupt
processing with direct interrupt service routine vector generation on a per-source basis.
Each source has programmability for masking, processor interrupt input, and priority.
XSI System Controller
EccbbpoouauanmtcsshhtpacrsoyrlXebflcSlrtlieooetIrrmrsabso.t/ubiTctossoohne(neu,nrnvnXXoeeiSrStcstsItIh.eadsdalyalnstttdaotheebstmhouaeusdctdoXahrnrS)ebtIsreitosbmrlualopetsrirl.oodpTnyarh,stoefaavraniXbdmSueXsIisSnsrItgeyhsqsAeytudsesedtmhesratmesrcseosfcdnrobotanurmdotsrldolrcerelyerlqecshurlse.aesTans,nhtdaodelernssXsdhSaXfaInrSradseImydasinddtedgamrtDeasasta
Inter-Processor Communication
Each Intel XScale^® processor can interrupt or issue a reset to the second Intel XScale^®
processor. Each processor can generate up to 32 interrupts to the second processor.
Timers
sTuhpep8o1rt3s4o8nesuwpaptocrhtdsotgwotimpreorgpreamr pmroacbeless3o2r.-bit ^{timers per processor. The 81348 also}
GPIO
TShTAeT8U1S34p8ininpcaliursd.es sixteen General-Purpose I/O (GPIO) pins, and eight ACTIVITY/
DInatteal^®sh8e1et348 ^{I/O Processor}
14
December 2007
Order Number: 315038-003US