81348 Datasheet, PDF (75/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Electrical Specifications—Intel^® 81348
4.3.6 PCI Express Differential Transmitter (Tx) Output Specifications
Table 28.
PCI Express* Rx Input Specifications
Symbol
Parameter
Min. Nom Max Units Notes
V_DIFFp-p
Differential input voltage
0.175
1.200 V 1
J_TOTAL
Total output jitter
0.65 UI 2
V_CM-AC
AC common mode
100 mV 3
T_Reye
Receiver eye opening
0.35
UI 4
RL-Diff_RX
Differential return loss
12
dB 5
RL-CM_TX
Common mode return loss
6
dB 5
Z_RX-OUT-DC DC differential output impedance
90 100 110 Ohm 6
Z_RX-Match-DC D+/D- impedance matching
-5
+5 % 7
V_RX-SQUELCH Squelch detect threshold
75
175 mV 8
Cin_RX
AC coupled
75
nf 9
L_SKEW-RX
Lane to lane skew at Rx
20 UI 10
Notes:
1. PSeeaekF-Pigeuarked1i2ff.erential voltage. V_DIFFp-p = 2 × V_RMAx. Measured at the package pins of the receiver.
2. Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver
device. A receiver must therefore tolerate any additional jitter generated by the package to the die.
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5. 50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
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this is based on a
Applicable during
nominal PCI Express* interconnect
active (L0) and Align states only.
differential
characteristic
impedance
of
100
Ω.
6. DC Differential Mode Impedance 100 Ω ±10% tolerance.
7. DC impedance matching between two lanes of a port.
8. Peak-to-Peak value. Measured at the pin of the receiver. Differential signal below this level will
indicate a squelch condition.
9. All receivers shall be AC coupled to the media.
10. Lane skew at the Receiver that must be tolerated.
December 2007
Order Number: 315038-003US
Intel^® 81348 I/ODParotacsehsesoert
75