81348 Datasheet, PDF (33/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Package Information—Intel^® 81348
Table 13.
Reset Strap Signals (Sheet 1 of 3)
Name
Count Type
BOOT_WIDTH_8#
1
Reset
Strap
DF_SEL[2:0]
3
RSetrsaept
CFG_CYCLE_EN#
1
Reset
Strap
HOLD_X0_IN_RST#
1
RSetrsaept
HOLD_X1_IN_RST#
1
RSetrsaept
MEM_FREQ[1:0]
2
RSetrsaept
EXT_ARB#
1
RSetrsaept
INTERFACE_SEL_PCIX# 1
RSetrsaept
PCIX_EP#
1
RSetrsaept
Description
PMBeImBooroytBBouost Wwiinddtho:wS.ets the default bus width for the PBI
0 = 8 bits wide
1_No=_te1_:6 bMitusxwedideon(tdoesfaigunltaml _Ao_[d₀e_]).
Ds_{NNNteoooovrtttaieee}cg_:::eeFpuDDDonFFFrc___ttsSSSioEEEanLLLs[[[sS210ige]]]nlemmmecdtuuu:xxxtoTeeehdddeeaoooscnnnehtttooosftusssrnaiiigggpcnnntsiaaaoslllneAAAlwe[[[987cit]]]thtihne8n1u3m48b.er of
S_Pre_oe_ceth_se_so“_rD_De_ev_vic_ee_loF_pu_en_rc_'stio_Mn_anS_ue_ale_l cfto”r oafdtdhietioI_nn_ate_l l_d®_et8_a1_ils3_.48 I/O
CiCnyotcnelrfeifgaRuceeratrrtyeiotbnriietCsiyscccolelneEfaignreuadbralietni:oAnDTecUtye(crPlmeCsiSnuRen[st2iwl] _{ChaeontndhfieHgrouPsratCtILioonckout}
Bit is cleared.
01 == CCoonnffiigguurraattiioonn creytcrlyeseennaabbleledd(default _mode)
• PteCrIm-XinIantteedrfwaciteh: _{aCorentfrigyusrtaattiouns.cycles} are claimed and
N^•ote^Pa:^{CcIomEMxuppxlreeetdsioson*nTItnLoPteswirgfinathcaelC:}A^oC[^no1^fni]^{gfuigruartaiotnionRerterqyuSetsattsurses(CulRtSin).}
HwohledthInetretlhXeSIcnatleel^®_{XSMcicarloep®}romciecsrsooprro0ceinssRoersneut:mDbeetre0rmisinheesld
in reset until the reset bit is cleared in the PCI Configuration
and Status Register.
01_No==_teHD_:ooldnMoiuntxhreeodsldeotnintoressigent _{a(ldAef[a2u]lt mode)}
wHinohrledetshIenettreutlnhXteiSlIctnhateleelr^®_{eXsSMecitcarbloeitp}^®_{irsomccielcesrasoroperrdo1cineinstshRoeersPneCutI:mCDboeentrefi1rgmuisrinaheteisolnd}
and Status Register.
0 = Hold in reset
1_No=_teD_:o nMoutxheodldonintoressigent _a(ldAef_[a₃u_]lt mode)
Memory Frequency: Determines frequency at which DDR2
memory subsystem runs.
00 = Reserved
011_NN101_oott===_eeR54_{::30es30eMMMMrvEEHHeMMzzd__(FFDRRefEEaQQu[[lt10m]] ommduuexx)eedd oonnttoo ssiiggnnaall AA[[54]]}
External Arbiter: Determines whether the PCI interface
enables the integrated arbiter, or use an external arbiter.
01_No==_teEI_{:nxtteeMrrnnuaaxlleaadrrbobinitteteorr (sdigenfaaul lAt [m6o]de)}
01 == PPCCII-EXxipsraecstsivise _{active (default mode)}
Wt_Nhoha_tet_enis_:bfouMtnhcutixinoetnder0ofanicntoetshsiaegrneinatalec_Artni[va₁el₀,a_]tdhdisresstsrampaspe.lects the ATU
PCI-X End Point: Determines whether the PCI-X interface
operates as an endpoint or a central resource.
0 = Endpoint
1_NNoo=_tteeC_::enMStreuatxlteirnedgsoobnuotrtoches_Pi(gCdne_IafXal_{_}u_AEl_[t_P1m_#1o_{]adned) PCIE_RC# to endpoint}
is unsupported.
December 2007
Order Number: 315038-003US
Intel^® 81348 I/ODParotacsehsesoert
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