81348 Datasheet, PDF (73/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Electrical Specifications—Intel^® 81348
4.3.4 I²C/SMBus Interface Signal Timings
Table 26.
I²C/SMBus Signal Timings
Symbol
Parameter
FSCL
T_BUF
T_HDSTA
T_LOW
THIGH
TSUSTA
THDDAT
TSUDAT
T_SR
SCL Clock Frequency
BCuosndFirteioenTime Between STOP and START
Hold Time (repeated) START Condition
SCL Clock Low Time
SCL Clock High Time
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
SCL and SDA Rise Time
Std. Mode
Min. Max
0 100
4.7
4
4.7
4
4.7
0 3.45
250
1000
T_SF SCL and SDA Fall Time
300
T_SUSTO Setup Time for STOP Condition
4
Notes:
21..
NSeoet tFeisgtuerde.13,
“I²C
Interface
Signal
Timings”
on
page
80.
3. After this period, the first clock pulse is generated.
54.. SCt^bd=MtohdeetIo^{2tCalsciagpnaacl ittiamnicnegsofaopnpelybfuosr lSinMeB,uins} tpiFm. ing.
Fast Mode
Min. Max
Units
Noste
0 400 KHz
1.3
µs (1)
0.6
µs (1,3)
1.3
µs (1,2)
0.6
µs (1,2)
0.6
µs (1)
0
0.9 µs (1)
100
ns (1)
20 +
0.1C_b
300
ns (1,4)
02.01C+_b ^{300 ns (1,4)}
0.6
µs (1)
December 2007
Order Number: 315038-003US
Intel^® 81348 I/ODParotacsehsesoert
73