81348 Datasheet, PDF (24/89 Pages) Intel Corporation – Two Integrated Intel XScale processors

Intel^® 81348—Package Information
Table 7.
Storage Interface Signals (Sheet 1 of 3)
Name
Count Type
Description
SS__CCLLKKNP00,
2
SS__TTXXNP[[77::00]],
16
SS__RRXXNP[[77::00]],
16
RBIAS[1:0]
2
R1:B0I]AS_SENSE[ ₂
SS_CALOCCT0K0/
1
SS_LOSTAADT00 /
1
S_ACT1
1
S_STAT1
1
SS_DAACTTA2IN/₀
1
SS_DSATTAATO2U/_T0
1
I
Diff
Storage Clock is the 125 MHz ±100 ppm differential input reference
c_Nlo_oc_tk_e:forSthhoeuilndtebrefaAcCe.coupled _{with a 100nF capacitor.}
O
Diff
Se_Nmtoo_tbreae_:gdedeTSdrhaconluoslmcdkibtfeocraArtCrhieecsoinutthpeelerfddaicfwfeei.trhenati1a0l _{noFutcpauptasceitroiar.l} data and
DIiff ^Se_N^mt_o^o_t^br_e^ae_:^{gdedeRSdehccoeluoilvcdekbcfeoarrArtCiheescoitnuhtpeelerdfdiaffcweeri.tehntaia1l0innpFuctaspearciaitlodr.ata and}
O ^{RcoensnisetcotreBdiabse:twAe6e.n49thKisΩ}p1in%an1d/8g^Ωrouexntderfnoralprreospiestroorpmeruasttiobne. This
resistor generates internal bias currents.
Resistor Bias Sense is used internally to sense ground. This ball
I/O m_RBu_Is_At b_Se_[1c_:o₀n_]nerecsteisdtotroisthceonsanmecetepdhytosicoanl _{tghreouPnCdB.point} as the
Stotodrraivgee _{aAnctLivEiDty:toWinhdenicaStGePaIcOt[iv0i]tyisodnistahbelelidn,ktfhoirs sptionracgaen} be used
OD
ed_Nnr_oigvtie_enn_:e[f0roC].monTanhneecSptiGnthPceIaOLn.EbDetdoiraecsterdierisverensbisytotrhepusltloerdagupe
engine or
to VCC.
Serial Clock: (default) When SGPIO[0] is enabled, this pin is the
S^sSeDC^{rLAiaOTl CAouKIt}N0^p0^{uis.t uclsoecdk trounlanticnhgSaLtO9A9.D80K,HSzD. AThTeAOfaUlliTn0g,eadngde of}
Storage Status: When SGPIO[0] is disabled this pin can be used to
OD
dpS_NriG_{onivPtceeIaO:}an.nbCLeEoDdninrteeoccittntddhriceivaeLtenEDsbtyatottuhasesoseftrotiherasegrlieenskeisnftogorirnseptouorlrlaegdderiuvepenngtoifnrVeoC[m0C].a.nThe
Ssseterrreiiaaalml _{lLo.oaaddc:lo(dcke.faIutlits) dWrihveenn} ShGigPhIOto[0in] _{disiceanteabthleed,sttahrits opfinthise} tbhite
Storage Activity: When SGPIO[0] is disabled, this pin can be used
OD
ted_Nonr_{oigvdtierenin:}vee[f1raoC]n.monTLanhEneeDcSpttiGonthPicneIaOdLni.cEbaDteetdoaircaeticsvteitrdyieriosvnerentshbiesytloitnrhkepufsoltlroerdsatogurpeaegtonegViCnCe.or
OD ^{SdpritniovrceaaganenbSLeEtaDdtiurteso:citnWddhricievanetenSGsbtPyaIttOuhs[e0o]sftiotshrdaeigslieanbkelnefogdri,nstehtoiosrrapgdienriveceannngifnbreeo[mu1s]ae.ndThtoe}
S_NG_oP_teIO_: . _{Connect the LED to a series resistor pulled up to VCC.}
Storage Activity: When SGPIO[0] is disabled, this pin can be used
OD
ted_Nonr_{oigvdtierenin:}vee[f2raoC]n.monTLanhEneeDcSpttiGonthPicneIaOdLni.cEbaDteetdoaircaeticsvteitrdyieriosvnerentshbiesytloitnrhkepufsoltlroerdsatogurpeaegtonegViCnCe.or
Serial Data In: (default) When SGPIO[0] is enabled, this pin is the
seeigrhiatldinepvuictedsaatrae. Tsuhpepreoratreed.three bits of data per device and up to
Storage Status: When SGPIO[0] is disabled, this pin can be used to
OD
dpS_NriG_{onivPtceeIaO:}an.nbCLeEoDdninrteeoccittntddhriceivaeLtenEDsbtyatottuhasesoseftrotiherasegrlieenskeisnftogorirnseptouorlrlaegdderiuvepenngtoifnrVeoC[m2C].a.nThe
Serial Data Out: (default) When SGPIO[0] is enabled, this pin is the
seeigrhiatldoeuvtpicuetsdaartea.suTphpeorertaerde. three bits of data per device and up to
DInatteal^®sh8e1et348 ^{I/O Processor}
24
December 2007
Order Number: 315038-003US