HYB18T1G400AF Datasheet, PDF (9/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.5 Input/Output Functional Description
Symbol
CK, CK
Type
Function
Clock: CK and CK are differential system clock inputs. All address and control inputs are sampled on the crossing of
Input ^{the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossing of CK and CK}
(both direction of crossing)
CKE
Input
Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device input buffers and out-
put drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active
Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for self-refresh entry.
Input buffers excluding CKE are disabled during self-refresh. CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous. After VREF has become stable during power-on and initiali-
sation sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are disabled during dower-down.
CS
Input
Chip Select: All command are masked when CS is registered high. CS provides for external rank selection on sys-
tems with multiple memory ranks. CS is considered part of the command code.
RAS, CAS, WE ^{Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered}
DM, LDM, UDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading. LDM and UDM are the input mask signals for x16 compo-
nents and control the lower or upper bytes. For x8 components the data mask function is disabled, when RDQS /
RQDS are enabled by EMRS(1) command.
Bank Address Inputs: BA0, BA1, BA2 define to which of the 8 internal memory banks an Activate, Read, Write or
BA0, BA1, BA2 ^{Input Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register}
is to be accessed during a MRS or EMRS cycle.
A0 - A13
Input
Address Inputs: Provides the row address for Activate commands and the column address and Auto-Precharge bit
A10 (=AP) for Read/Write commands to select one location out of the memory array in the respective bank. A10
(=AP) is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10=low)
or all banks (A10=high). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The
address inputs also provide the op-code during Mode Register Set commands.
Row address A13 is used on x4 and x8 components only.
DQx,
Input/ Data Inputs/Output: Bi-directional data bus. DQ0~DQ3 for x4 components, DQ0~DQ7 for x8 components,
LDQx,UDQx Output ^{LDQ0~LDQ7 and UDQ0~UDQ7 for x16 components}
DQS, (DQS)
Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For
LDQS, (LDQS),
UDQS,(UDQS)
Input/
Output
the x16, LDQS corresponds to the data on LDQ0 - LDQ7; UDQS corresponds to the data on UDQ0-UDQ7. The data
strobes DQS, LDQS, UDQS may be used in single ended mode or paired with the optional complementary signals
DQS, LDQS, UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1)
control bit enables or disables the complementary data strobe signals.
RDQS, (RDQS)
Input/
Output
Read Data Strobe: For the x8 components a RDQS, RDQS pair can be enabled via the EMRS(1) for read timing.
RDQS, RDQS is not supported on x4 and x16 components. RDQS, RDQS are edge-aligned with read data. If
RDQS, RDQS is enabled, the DM function is disabled on x8 components.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is applied to each DQ, DQS, DQS and DM signal for x4 and DQ, DQS, DQS, RDQS, RDQS and DM
for x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and
LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.
NC
No Connect: no internal electrical connection is present
VDDQ
Supply DQ Power Supply: 1.8V +/- 0.1V
VSSQ
Supply DQ Ground
VDDL
Supply DLL Power Supply: 1.8V +/- 0.1V
VSSDL
Supply DLL Ground
VDD
Supply Power Supply: 1.8V +/- 0.1V
VSS
Supply Ground
VREF
Supply Reference Voltage
(A14~A15)
- A14 ~ A15 are additional address pins for future generation DRAMs and are not connected on this component.
Page 9
Rev. 1.02
May 2004
INFINEON Technologies