HYB18T1G400AF Datasheet, PDF (22/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the follow-
ing timing diagram. Input data pattern for adjustment, DT0 - DT3 is fixed and not affected by MRS addressing
mode (i.e. sequential or interleave). Burst length of 4 have to be programmed in the MRS for OCD impedance
adjustment.
CK, CK
CM D _{EM RS(1)}
NOP
NOP
NOP
NOP
WL
DQS
D Q S _in
DQ _in
tDS tDH
DT0 DT1 DT2 DT3
DM
OCD adjust mode
NOP
NOP
tW R
EM RS(1)
NOP
OCD calibration
mode exit
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance
before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” com-
mand and all output drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing
diagram.
CK, CK
CM D _{EM RS(1)}
NOP
NOP
NOP
NOP
EM R S(1)
NOP
NOP
tOIT
tOIT
DQ S_in
DQ _in
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
DQS high for Drive(1)
DQS high for Drive(0)
Enter Drive Mode
OCD calibration
mode exit
Page 22
Rev. 1.02
May 2004
INFINEON Technologies