HYB18T1G400AF Datasheet, PDF (25/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
ODT Timing for Active and Standby (Idle) Modes
(Synchronous ODT timings)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
C K E see note 1
ODT
t_IS
t_IS
tAOND (2 tck)
tAOFD (2.5 tck)
Rtt
DQ
tAON(min)
tAOF(min)
tAON(max)
tAOF(max)
ODT01
1) Synchronous ODT timings apply for Active Mode and Standby Mode with CKE “high” and for the “Fast Exit” Active Power Down
Mode (MRS bit A12 set to “0”). In all these modes the on-die DLL is enabled.
2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on
time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND.
3) ODT turn off time min. (tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF,max) is
when the bus is in high impedance. Both are measured from tAOFD.
ODT Timing for Precharge Power-Down and Active Power-Down Mode (with slow exit)
(Asynchronous ODT timings)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CKE
"low"
t_IS
ODT
t_IS
tAOFPD,min
tAOFPD,max
DQ
Rtt
tAONPD,min
tAONPD,max
ODT02
1) Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down Mode (MRS bit A12 set to
“1”), where the on-die DLL is disabled in this mode of operation.
Page 25
Rev. 1.02
May 2004
INFINEON Technologies