HYB18T1G400AF Datasheet, PDF (30/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.6.1 Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2
SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the
RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is
held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the
sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the
tRCDmin, then AL greater than 0 must be written into the EMRS(1). The Write Latency (WL) is always defined as
RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency
(RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also
defined as RL = AL + CL.
Examples:
Read followed by a write to the same bank, Activate to Read delay < tRCDmin:
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
0 1 2 34 5
CK, CK
CMD
DQS,
DQS
DQ
Activate Read
Bank A Bank A
AL = 2
Write
Bank A
CL = 3
tRCD
RL = AL + CL = 5
678
WL = RL -1 = 4
Dout0 Dout1 Dout2 Dout3
9 10 11
Din0 Din1 Din2 Din3
PostCAS1
Read followed by a write to the same bank, Activate to Read delay < tRCDmin:
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
0 1 2 34 5
CK, CK
CMD
DQS,
DQS
DQ
Activate Read
Bank A Bank A
AL = 2
CL = 3
tRCD
RL = AL + CL = 5
6 7 8 9 10 11 12
Write
Bank A
WL = RL -1 = 4
Dout0 Dout1 Dout2 Dout3 Dout4 Dout5 Dout6 Dout7
Din0 Din1 Din2 Din3
PostCAS3
Page 30
Rev. 1.02
May 2004
INFINEON Technologies