HYB18T1G400AF Datasheet, PDF (19/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.2.5 EMRS(2) Extended Mode Register
The Extended Mode Registers EMRS(2) and EMRS(3) are reserved for future use and must be programmed
when setting the mode register during initialization.
The extended mode register EMRS(2) is written by asserting low on CS, RAS, CAS, WE, BA2, BA0 and high on
BA1, while controlling the state of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD)
must be satisfied to complete the write operation to the EMRS(2). Mode register contents can be changed using
the same command and clock cycle requirements during normal operation as long as all banks are in precharge
state.
BA2 BA1 BA0 A13~A15 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0* 1 0
0*
*) must be programmed to "0"
Address Field
Extended Mode
Register(2)
EMRS(2)
2.2.6 EMRS(3) Extended Mode Register
The Extended Mode Register EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be pro-
grammed to 0 when setting the mode register during initialization
.
BA2 BA1 BA0 A13~A15 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0* 1 1
0*
*) must be programmed to "0"
Address Field
Extended Mode
Register(3)
Page 19
Rev. 1.02
May 2004
INFINEON Technologies