HYB18T1G400AF Datasheet, PDF (33/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.6.3 Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The delay from the
start of the command until the data from the first cell appears on the outputs is equal to the value of the read
latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the
data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent
data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to
an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is
defined by the Extended Mode Register Set (EMRS(1)).
Basic Burst Read Timing
CLK, CLK
CLK
CLK
DQS,
DQS
DQ
t _CH t _CL
t _CK
t _DQSCK
t _AC
DQS
DQS
t _RPRE
t _LZ
tRPST
t _HZ
t DQSQmax
Dout
t QH
Dout
Dout
Dout
t _DQSQmax
t QH
DO-Read
Examples:
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Post CAS
NOP
READ A
DQS,
DQS
DQ
AL = 2
NOP
NOP
RL = 5
CL = 3
NOP
NOP
NOP
<= tDQSCK
NOP
Dout A0 Dout A1 Dout A2 Dout A3
NOP
BRead523
Page 33
Rev. 1.02
May 2004
INFINEON Technologies