HYB18T1G400AF Datasheet, PDF (47/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.8 Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2
SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automati-
cally begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the
Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains
active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then
the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will execute as normal with
the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency (CL)
clock cycles before the end of the read burst. Auto-Precharge is also implemented for Write Commands.The Pre-
charge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst
sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or
completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance
for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore
operation has been completed so that the Auto-Precharge command may be issued with any read or write com-
mand.
2.8.1 Burst Read with Auto-Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2
SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read
with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of
Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTPmin is not satisfied at the edge, the
start point of Auto-Precharge operation will be delayed until tRTPmin is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens
(not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge
to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to
the next Activate command is AL + 2 + tRTP + tRP. Note that (tRTP + tRP) has to be rounded up to the next inte-
ger value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simul-
taneously:
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Page 47
Rev. 1.02
May 2004
INFINEON Technologies