HYB18T1G400AF Datasheet, PDF (24/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
ODT Truth Tables
The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and
A11 in the EMRS(1) for all three device organisations (x4, x8 and x16). To activate termination of any of these
pins, the ODT function has to be enabled in the EMRS(1) by address bits A6 and A2.
Input Pin
EMRS(1)
EMRS(1)
Address Bit A10 Address Bit A11
x4 components:
DQ0~DQ3
X
X
DQS
X
X
DQS
0
X
DM
X
X
x8 components:
DQ0~DQ7
X
X
DQS
X
X
DQS
0
X
RDQS
X
1
RDQS
0
1
DM
X
0
x16 components:
LDQ0~LDQ7
X
X
UDQ0~UDQ7
X
X
LDQS
X
X
LDQS
0
X
UDQS
X
X
UDQS
0
X
LDM
X
X
UDM
X
X
X = don’t care; 0 = bit set to low; 1 = bit set to high
ODT timing modes
Depending on the operating mode synchronous or asynchronous ODT timings apply. Synchronous timings
(tAOND, tAOFD, tAON and tAOF) apply for all modes, when the on-die DLL is not disabled.
These modes are:
Active Mode
Standby Mode
Fast Exit Active Power Down Mode (with MRS bit A12 is set to “0”)
Asynchronous ODT timings (tAOFPD, tAONPD) apply when the on-die DLL is disabled.
These modes are:
Slow Exit Active Power Down Mode (with MRS bit A12 is set to “1”)
Precharge Power Down Mode
Page 24
Rev. 1.02
May 2004
INFINEON Technologies