HYB18T1G400AF Datasheet, PDF (88/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
11. Content
1. Description
1.1 Ordering Information
1.2 Pin Description
1.3 DDR2 SDRAM Addressing
1.4 Package Pinouts
1.5 Input / Output Functional Description
1.6 Block Diagrams
2. Functional Description
2.1 Simplified State Diagram
2.2 Basic Functionality
2.2.1 Power-On and Initialization
2.2.2 Programming the Mode Registers
2.2.3 Mode Register Set (MRS)
2.2.4 Extended Mode Register Set (EMRS(1))
2.2.5 Extended Mode Register Set (EMRS(2))
2.2.6 Extended Mode Register Set (EMRS(3))
2.3 Off-Chip Driver (OCD) Impedance Adjustment
2.4 ODT On-Die Active Termination
2.5 Bank Activate Command
2.6 Read and Write Command
2.6.1 Posted CAS
2.6.2 Burst Mode Operation
2.6.3 Burst Read Operation
2.6.4 Burst Write Operation
2.6.5 Write Data Mask
2.6.6 Burst Interruption
2.7 Precharge Command
2.7.1 Burst Read Operation followed by a Precharge
2.7.2 Burst Write Operation followed by a Precharge
2.8 Auto-Precharge Command
2.8.1 Read with Auto-Precharge
2.8.2 Write with Auto-Precharge
2.8.3 Read or Write to Precharge Command Spacing Summary
2.8.4 Concurrent Auto-Precharge
2.9 Refresh Commands
2.9.1 Auto-Refresh Command
2.9.2 Self-Refresh Command
2.10 Power-Down
2.11 Other Commands
2.11.1 No Operation
2.11.2 Deselect
2.12 Input Clock Frequency Change
2.13 Asynchronous CKE Low Event
3. Truth Tables
3.1 Command Truth Table
3.2 Clock Enable (CKE) Truth Table
3.3 Data Mask (DM) Truth Table
4. Operating Conditions
4.1 Absolute Maximum Ratings
4.2 DRAM Component Operating Temperature Range
Page 88
Rev. 1.02
May 2004
INFINEON Technologies