HYB18T1G400AF Datasheet, PDF (84/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
8.3.4 Input Setup (tIS) and Hold (tIH) Time Derating Table
CK, CK Differential Slew Rate
2.0 V/ns
∆ tIS
∆ tIH
1.5 V/ns
∆ tIS
∆ tIH
1.0 V/ns
∆ tIS
∆ tIH
Unit
4.0
+187
+94
+217
+124
+247
+154
ps
3.5
+179
+89
+209
+119
+239
+149
ps
3.0
+167
+83
+197
+113
+227
+143
ps
2.5
+150
+75
+180
+105
+210
+135
ps
2.0
+125
+45
+155
+75
+185
+105
ps
1.5
+83
+21
+113
+51
+143
+81
ps
1.0
0
0
+30
+30
+60
+60
ps
0.9
-11
-14
+19
+16
+49
+46
ps
0.8
-25
-31
+5
-1
+35
+29
ps
0.7
-43
-54
-13
-24
+17
+6
ps
0.6
-67
-83
-37
-53
-7
-23
ps
0.5
-110
-125
-80
-95
-50
-65
ps
0.4
-175
-188
-145
-158
-115
-128
ps
0.3
-285
-292
-255
-262
-225
-232
ps
0.25
-350
-375
-320
-345
-290
-315
ps
0.2
-525
-500
-495
-470
-465
-440
ps
0.15
-800
-708
-770
-678
-740
-648
ps
0.1
-1450
-1125
-1420
-1095
-1390
-1065
ps
1. For all input signals the total tIS (input setup time) and tIH (input hold time) required is calculated by adding the individual
datasheet value to the derating value listed in the previous table.
2. For slow slewrate the total setup time might be negativ (i.e. a valid input signal will not have reached VIH(ac) / VIL(ac) at the
time of the rising clock) a valid input signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew
rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. These val-
ues are not subject to production test. They are verified only by design and characterisation.
8.3.5 Data Setup (tDS) and Hold Time (tDH) Derating Tablefor differential DQS / DQS
DQS, DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH Unit
2.0 +125 +45 +125 +45 +125 +45 ^{- -} - - - - - - - - - - ps
1.5 +83 +21 +83 +21 +83 +21 +95 +33 - - - - - - - - - - ps
1.0 0 0 0 0 0 0 +12 +12 +24 +24 - - - - - - - - ps
0.9 - - -11 -14 -11 -14 +1 -2 +13 +10 +25 +22 - - - - - - ps
0.8 - - - - -25 -31 -13 -19 -1 -7 +11 +5 +23 +17 - - - - ps
0.7 - - - - - - -31 -42 -19 -30 -7 -18 +5 -6 +17 +6 - - ps
0.6 - - - - - - - - -43 -49 -31 -47 -19 -35 -7 -23 +5 -11 ps
0.5 - - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53 ps
0.4 - - - - - - - - - - - - -127 -140 -115 -128 -103 -116 ps
1. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual datasheet value to the der-
ating value listed in the previous table.
2. For slow slewrate the total setup time might be negativ (i.e. a valid input signal will not have reached VIH(ac) / VIL(ac) at the time of the ris-
ing DQS) a valid input signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in between the values
listed in the next tables, the derating values may be obtained by linear interpolation. These values are not subject to production test. They
are verified only by design and characterisation.
Page 84
Rev. 1.02
May 2004
INFINEON Technologies