HYB18T1G400AF Datasheet, PDF (54/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.9.2 Self-Refresh Command
The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in
the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has
a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined by having CS,
RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing
Self Refresh command, by either driving ODT pin low or using EMRS(1) command. Once the command is regis-
tered, CKE must be held low to keep the device in Self-Refresh mode. The DLL is automatically disabled upon
entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the DDR2 SDRAM has
entered Self-Refresh mode all of the external control signals, except CKE, are “don’t care”. The DRAM initiates a
minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode. The clock
is internally disabled during Self-Refresh Operation to save power. The minimum time that the DDR2 SDRAM
must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external
clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the
device can exit Self-Refresh operation.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to
CKE going back HIGH. Once Self-Refresh Exit command is registered, a delay of at least tXSNR must be satis-
fied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must
remain high for the entire Self-Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the
DDR2 SDRAM can be put back into Self Refresh mode after tXSNR expires. NOP or deselect commands must be
registered on each positive clock edge during the Self-Refresh exit interval tXSNR. ODT should be turned off dur-
ing tXSRD.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when
CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a mini-
mum of one extra auto refresh command before it is put back into Self Refresh Mode.
T0
T1
CK/CK
CKE
tis
ODT
T2
T3
T4
T5
tRP*
tis
tAOFD
tCKE
Tm
Tn
Tr
tis
>=tXSRD
>= tXSNR
CMD
Self R efresh
E n try
NOP
N o n -R e a d
Command
Read
Com mand
CK/CK may
be halted
CK/CK must
be stable
* = Device must be in the “All banks idle” state before entering Self Refresh mode.
tXSRD (>=200 tCK) has to be satisfied for a Read or a Read with Auto-Precharge command.
tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command
Since CKE is an SSTL input, VREF must be maintained during Self Refresh.
Page 54
Rev. 1.02
May 2004
INFINEON Technologies