HYB18T1G400AF Datasheet, PDF (17/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.2.4 DDR2 SDRAM Extended Mode Register Set (EMRS(1))
The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength,
additive latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default
value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be writ-
ten after power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS,
WE, BA1, BA2 and high on BA0, while controlling the state of the address pins. The DDR2 SDRAM should be in
all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set
command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register con-
tents can be changed using the same command and clock cycle requirements during normal operation as long as
all banks are in precharge state.
EMRS(1) Extended Mode Register Operation Table (Address Input For Mode Set)
BA2 BA1 BA0 A13~A15 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0* 0* 1
0* Qoff RDQS DQS OCD program Rtt
Additive latency Rtt D.I.C DLL
Address Field
Extended Mode
Register
A 11 RDQS,(RQDS) Enable
0
D is a b le
1
E n a b le
A12
Qoff ^a)
0 Output buffers enabled
1 Output buffers disabled
a) Disables DQ, DQS, DQS, RDQS, RDQS
BA1 BA0
00
01
10
11
MRS mode
MRS
E M R S (1)
EMRS(2)
EMRS(3)
A6 A2 Rtt (nom.)
0 0 O DT disabled
0 1 75 ohm
1 0 150 ohm
1 1 Reserved
A 10 DQS,(RDQS) Disable
0
Enable
1
D is a b le
A0 DLL Enable
0
E n a b le
1
D is a b le
A5 A4 A3 AdditiveLatency
000
0
001
1
010
2
011
3
100
4
101
R e s erv e d
110
R e s erv e d
111
R e s erv e d
A9 A8 A7 O CD C alibration Program
0
0
0 OCD Cal. Mode Exit, maintain setting
001
Drive (1)
A1
O utput Driver
Impedence Control
010
100
Drive (0)
A d ju s t m o d e ^a)
0
N orm a l
1
W eak
1
1
1 OCD Calibration default ^b)
a) When Adjust mode is issued, AL from previously set value must be applied
b) After setting to default, OCD mode needs to be exited by setting A9~A7 to 000.
Refer to the following 2.2.2.5 section for detailed information.
*) must be programmed to 0 for compatibility with future DDR2 memory products.
D riv e r
S iz e
100%
60%
Page 17
Rev. 1.02
May 2004
INFINEON Technologies