HYB18T1G400AF Datasheet, PDF (23/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.5 On-Die Termination (ODT)
ODT (On-Die Termination) is a new feature on DDR2 components that allows a DRAM to turn on/off termination
resistance for each DQ, DQS, DQS and DM for x4 and DQ, DQS, DQS, DM, RDQS (DM and RDQS share the
same pin), and RDQS for x8 configuration via the ODT control pin, where DQS is terminated only when enabled in
the EMRS(1) by address bit A10 = 0. For x8 configuration RDQS is only terminated, when enabled in the
EMRS(1) by address bits A10 = 0 and A11 = 1.
For x16 configuration ODT is applied to each UDQ, LDQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
the ODT control pin, where UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit
A10 = 0.
The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to
independently turn on/off termination resistance for any or all DRAM devices.
The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-
Refresh mode.
Functional Representation of ODT
VDDQ
VDDQ
sw1
sw2
DRAM
Input
Buffer
Rval1
Rval2
Rval1
Rval2
Input
Pin
sw1
sw2
VSSQ
VSSQ
Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by “Rtt (nominal)” in
EMRS(1) address bits A6 & A2. Target Rtt = 0.5 * Rval1 or 0.5 * Rval2.
The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.
Page 23
Rev. 1.02
May 2004
INFINEON Technologies