HYB18T1G400AF Datasheet, PDF (12/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
CKE
CK
CK
CS
WE
CAS
RAS
AP
A0-A12,
BA0-BA2
Bank7
Bank2
Bank1
CK, CK
Mode
Registers
16
16
16
8192
Bank0
Memory
Array
(8192 x 256 x 64)
Sense Amplifiers
8
2
I/O Gating
DM Mask Logic
16
2
8
256
(x64)
8
10 ^{Column-Address}
Counter/Latch
2
Column
Decoder
COL0
DLL
Data
64
64
64
16
16
16
16
16
DQS
Generator
COL0,1 _Input
Register
Write ^{Mask 2}
2
FIFO
&
2
2
Drivers
2
2
8
2
2
1
DQS
DQS
2
16
16
64
16
Data ₁₆
16
16
16
16
16
CK,
CK
COL0,1
LDQ0-LDQ7
LDM
UDQ0-UDQ7
UDM
LDQS
LDQS
UDQS
UDQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation
of the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the
Block Diagram 16Mbit x 16 I/O x 4 Internal Memory Banks
(32Mb x 16 Organisation with 13 Row, 3 Bank and 11 Column External Addresses)
Page 12
Rev. 1.02
May 2004
INFINEON Technologies