HYB18T1G400AF Datasheet, PDF (11/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
CKE
CK
CK
CS
WE
CAS
RAS
AP
A0-A13,
BA0-BA2
Bank1
Bank0
Bank7
CK, CK
Mode
Registers
17
17
17
2
17
2
10 ^{Column-Address}
Counter/Latch
16384
Bank0
Memory
Array
(16384 x256x32)
Sense Amplifiers
8
I/O Gating
DM Mask Logic
8
256
(x32)
Column
Decoder
8
COL0,1
2
DLL
Data
32
32
32
8
8
8
8
8
DQS
Generator
COL0,1 _Input
Register
Write ^{Mask 1}
1
FIFO
&
1
1
Drivers
1
1
4
1
1
1
DQS
DQS
1
8
8
32
8
Data ₈
8
8
8
8
8
CK,
CK
COL0,1
DQ0-DQ7,
DM
DQS
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Block Diagram 32Mbit x 8 I/O x 4 Internal Memory Banks
(64Mb x 8 Organisation with 14 Row, 3 Bank and 11 Column External Addresses)
Page 11
Rev. 1.02
May 2004
INFINEON Technologies