HYB18T1G400AF Datasheet, PDF (51/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
Burst Write with Auto-Precharge (WR + tRP Limit): WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4
T0
T3
T4
T5
T6
T7
T8
T9
T12
CK, CK
CMD
P osted CAS
W RITE w/AP
NOP
A10 ="high"
DQS,
DQS
WL = RL-1 = 4
DQ
NOP
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
Auto-Precharge Begins
DIN A0 DIN A1 DIN A2 DIN A3
WR
tRP
tDAL
>=tRC
>=tRAS
Bank A
A ctivate
BW-AP423
2.8.3 Read or Write to Precharge Command Spacing Summary
The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to
the Precharge commands to the same banks and Precharge-All commands.
From Command
To Command
Minimum Delay between “From
Command” to “To Command”
Units Notes
READ
PRECHARGE (to same banks as READ)
PRECHARGE-ALL
AL + BL/2 + max(tRTP, 2) - 2*tck
AL + BL/2 + max(tRTP, 2) - 2*tck
tCK 1, 2
tCK 1, 2
READ w/AP
PRECHARGE (to same banks as READ w/AP)
PRECHARGE-ALL
AL + BL/2 + max(tRTP, 2) - 2*tck
AL + BL/2 + max(tRTP, 2) - 2*tck
tCK 1, 2
tCK 1, 2
WRITE
PRECHARGE (to same banks as WRITE)
PRECHARGE-ALL
WL + BL/2 + tWR
WL + BL/2 + tWR
tCK
2
tCK
2
WRITE w/AP
PRECHARGE (to same banks as WRITE w/AP)
PRECHARGE-ALL
WL + BL/2 + WR
WL + BL/2 + WR
tCK
2
tCK
2
PRECHARGE
PRECHARGE (to same banks as PRECHARGE)
PRECHARGE-ALL
1*tck
1*tck
tCK
2
tCK
2
PRECHARGE-ALL
PRECHARGE
PRECHARGE-ALL
1*tck
1*tck
tCK
2
tCK
2
Note 1: RTP[cycles] = RU{tRTP(ns) / tCK(ns)}, where RU stands for round up.
Note 2: For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or
precharge-all, issued to that bank. The precharge period is satisfied after tRP or tRPall depending on the latest prechargte com-
mand issued to that bank
Page 51
Rev. 1.02
May 2004
INFINEON Technologies