HYB18T1G400AF Datasheet, PDF (8/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.4.3 Package Pinout for x16 components 84 pins + 8 support pins, FBGA-92 Package (top view)
1
2
3
7
8
9
NC
NC
A
NC
NC
B
C
VDD
NC
VSS
D
VSSQ UDQS VDDQ
UDQ6 VSSQ UDM
E
UDQS VSSQ UDQ7
VDDQ UDQ1 VDDQ
F
VDDQ UDQ0 VDDQ
UDQ4 VSSQ DQ3
G
UDQ2 VSSQ UDQ5
VDD
NC
VSS
H
VSSQ LDQS VDDQ
LDQ6 VSSQ LDM
J
LDQS VSSQ LDQ7
VDDQ LDQ1 VDDQ
K
VDDQ LDQ0 VDDQ
LDQ4 VSSQ LDQ3
L
LDQ2 VSSQ LDQ5
VDDL VREF VSS
M
VSSDL CK
VDD
CKE
WE
N
RAS
CK
ODT
BA2
BA0
BA1
P
CAS
CS
A10
A1
R
A2
A0
VDD
VSS
A3
A5
T
A6
A4
A7
A9
U
A11
A8
VSS
VDD
A12 NC,(A14)
V
NC,(A15) NC,(A13)
W
X
NC
NC
AA
NC
NC
Notes:
1) UDQS/UDQS is data strobe for upper byte, LDQS/LDQS is data strobe for lower
byte
2) UDM is the data mask signal for the upper byte UDQ0~UDQ7,
LDM is the data mask signal for the lower byte LDQ0~LDQ7
3) NC,(A13), NC,(A14) and NC,(A15) are additional address pins for future genera-
tion DRAMs and are not connected on this component.
Page 8
Rev. 1.02
May 2004
INFINEON Technologies