HYB18T1G400AF Datasheet, PDF (35/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
Seamless Burst Read Operation: RL = 5, AL = 2, CL = 3, BL = 4
T0
T1
T2
T3
T4
T5
CK, CK
CMD ^{Post CAS}
READ A
NOP
Post CAS
READ B
NOP
NOP
NOP
T6
NOP
T7
NOP
T8
NOP
DQS,
DQS
DQ
AL = 2
CL = 3
RL = 5
Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3
SBR523
The seamless burst read operation is supported by enabling a read command at every BL / 2 number of clocks.
This operation is allowed regardless of same or different banks as long as the banks are activated.
Seamless Burst Read Operation: RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
CMD Post CAS
READ A
NOP
NOP
NOP
Post CAS
READ B
NOP
NOP
NOP
NOP
NO
DQS,
DQS
DQ
CL = 3
RL = 3
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A4 Dout A7 Dout B0 Dout B1 Dout B2 Dout B3 Dou
SBR_BL8
The seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every BL /
2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are acti-
vated.
Page 35
Rev. 1.02
May 2004
INFINEON Technologies