HYB18T1G400AF Datasheet, PDF (37/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
Burst Write Operation: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
T0
T1
T2
T3
T4
T5
T6
CK, CK
CMD Post CAS
NOP
W R ITE A
DQS,
DQS
DQ
WL = RL-1 = 2
NOP
NOP
<= tDQSS
NOP
NOP
NOP
Com pletion of
the Burst W rite
DIN A0 DIN A1 DIN A2 DIN A3
tW R
T7
T9
P re c h a rg e
Bank A
A c tiv a te
tR P
BW322
Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
W rite to Read = (CL - 1)+ BL/2 +tW TR(2) = 6
CMD
NOP
NOP
NOP
NOP
Post CAS
READ A
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL - 1 = 4
DIN A0 DIN A1 DIN A2 DIN A3
AL=2
tW TR
CL=3
RL=5
BWBR
The minimum number of clocks from the burst write command to the burst read command is
(CL - 1) +BL/2 + tWTR
where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recov-
ery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the
array.
Page 37
Rev. 1.02
May 2004
INFINEON Technologies