HYB18T1G400AF Datasheet, PDF (7/89 Pages) Infineon Technologies AG – 1 Gbit DDR2 SDRAM

HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.4.2 Package Pinout for x8 components, 60 pins + 8 support pins, FBGA-68 Package (top view)
1
2
3
NC
NC
VDD
DQ6
VDDQ
DQ4
VDDL
BA2
VSS
VDD
NU,
RDQS
VSS
VSSQ
DM,
RDQS
DQ1 VDDQ
VSSQ DQ3
VREF VSS
CKE
WE
BA0
BA1
A10
A1
A3
A5
A7
A9
A12 NC,(A14)
NC
NC
Notes:
7
8
9
A
NC
NC
B
C
D
E
VSSQ DQS VDDQ
F
DQS VSSQ DQ7
G
VDDQ DQ0 VDDQ
H
DQ2 VSSQ DQ5
J
VSSDL CK
VDD
K
RAS
CK
ODT
L
CAS
CS
M
A2
A0
VDD
N
A6
A4
P
A11
A8
VSS
R
NC,(A15) A13
T
U
V
W
NC
NC
1) RDQS / RDQS are enabled by EMRS(1) command.
2) If RDQS / RDQS is enabled, the DM function is disabled
3) When enabled, RDQS & RDQS are used as strobe signals during reads.
4) VDDL and VSSDL are power and ground for the DLL. They are isolated on the
device from VDD, VDDQ, VSS and VSSQ.
5) NC,(A14) and NC,(A15) are additional address pins for future generation DRAMs
and are not connected on this component.
Page 7
Rev. 1.02
May 2004
INFINEON Technologies