HYB18RL25632AC Datasheet, PDF (9/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Note: NC : No Connect : These signals are internally connected and have parasitic characterisitcs of an IO. They may optionally be
connected to ground for improved heat dissipation.
1.3.1 Ball Description
Table 2 Ball description
Ball
CK, CK#
CS#
AS#, WE#,
REF#
A[19:0]
BA[0:2]
DQ[31:0]
DQSx,
DQSx#
DVLD
DM0, DM1
TCK
TMS, TDI
TDO
VREF
VEXT
VDD
VDDQ
VSS
VSSQ
Type
Detailed Function
Input Clock: CK and CK# are differential clock inputs. Addresses and commands are
Input latched on the rising edge of CK, input data is latched on the both edges of CK. CK# is
ideally 180 degrees out of phase with CK.
Chip Select: CS# enables the command decoder when low and disables it when high.
Input When the command decoder is disabled new commands are ignored, but internal
operations continue.
Input
Command Inputs: Sampled at the positive edge of CK. AS#, WE# and REF# define
(together with CS#) the command to be executed.
Input
Address Inputs: A[19:0] define the row and column addresses for READ and WRITE
operations. During an MODE REGISTER SET the address inputs A[17:0] define the
register settings. The addresses are sampled at the rising edge of CK. In the x32
configuration, A[19] is not used. In the x16 configuration with BL2, A[19] is used.
Input Bank select: Select to which internal bank a command is being applied.
Input/
Output
Data Input / Output: The DQ signals form the 32 bit data bus. During READ commands the
data is referenced to both edges of DQS/DQS#. During WRITE commands the data is
sampled at both edges of CK.
Output
Data read strobes : DQSx and DQSx# are the differential data read strobes. During
READs, they are transmitted by the RLDRAM and edge-aligned with data. DQSx is ideally
180 degrees out of phase with DQSx#. DQS0, DQS0# are aligned with DQ0-DQ7. DQS1,
DQS1# are aligned with DQ8-DQ15. DQS2, DQS2# are aligned with DQ16-DQ23. DQS3,
DQS3# are aligned with DQ24-DQ31.
Output
Data Valid: The DVLD indicates valid output data. DVLD is edge-aligned with DQSx,
DQSx#.
Input
Data Mask: DM0 and DM1 are the input masks for WRITE data. The first half of the Input
data burst is masked when DM0 is sampled HIGH along with the WRITE command. The
second half of the input data burst is masked when DM1 is sampled HIGH along with the
WRITE command.
Input
IEEE 1149.1 Clock Input: JEDEC standard 1.8V IO levels. These pin must be tied to VSS
if the JTAG function is not used in the circuit.
Input
IEEE 1149.1 Test Inputs: JEDEC standard 1.8V IO levels. These pins may be left not
connected if the JTAG function is not used in the circuit.
Output IEEE 1149.1 Test Output: JEDEC standard 1.8V IO level tracking VDDQ.
Supply
Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input
buffers.
Supply
Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions
for range.
Supply
Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions
for range.
Supply
Power Supply: Isolated Output Buffer Supply. 1.8V nominal. See DC Electrical
Characteristics and Operating Conditions for range.
Supply Power Supply: GND
Supply Power Supply: Isolated Output Buffer Supply. GND
Version 1.60
Page 9
Infineon Technologies
This specification is preliminary and subject to change without notice