HYB18RL25632AC Datasheet, PDF (28/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3 IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM incorporates a serial boundary scan Test Access Port (TAP). This port operates fully
complient with IEEE Standard 1149.1-1990. It contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID code register.
It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP controller, TCK
must be tied low while TDI, TMS and TDO may be left unconnected. Upon power-up, the TAP will come up
in a reset state which will not interfere with the normal operation of the device.
3.1 Test Access Port (TAP)
3.1.1 Test Clock (TCK)
The test clock is used only with the TAP controller. The pin must be tied low if the TAP is not used.
3.1.2 Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK.
This pin may be left unconnected if the TAP is not used.
3.1.3 Test Data-In (TDI)
The TDI pin is used to serially input information into the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most
significant bit (MSB) of any register (see Figure 27). This pin may be left unconnected if the TAP is not used.
3.1.4 Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon
the current state of the TAP state machine (see Figure 28). The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register (see Figure 27). This pin may be left
unconnected if the TAP is not used.
3.2 TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and shifted out
of the RLDRAM test circuitry (see Figure 27). Only one register is selected at a time through the instruction
register. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
3.2.1 Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in Figure 27. Upon power-up, the instruction register is
internally preloaded with the IDCODE instruction.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01"
pattern to allow for fault isolation of the board-level serial test data path.
3.2.2 Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO pins. This allows
data to be shifted through the RLDRAM with minimal delay.
The bypass register is set LOW during the Capture-DR state when the BYPASS instruction is loaded in the
instruction register.
Version 1.60
Page 27
Infineon Technologies
This specification is preliminary and subject to change without notice