HYB18RL25632AC Datasheet, PDF (17/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.3 Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of
the memory. It programs the RLDRAM configuration, burst length, test
mode and IO options. During a Mode Register Set command the address
inputs A<17:0> are sampled and stored in the mode register. tMRSC
must be met before any command can be issued to the RLDRAM. The
mode register may be set anytime as long as all command are
completed, and the RLDRAM is in an idle state (no persistent
commands).
Figure 9 Mode Register Set Timing
CK#
CK
Command MRS
NOP
NOP
A.C.
t_MRSC
MRS:
command
A.C.:
MRS
Any command
Don't Care
Figure 8
Mode Register Set
CK#
CK
CS#
AS#
WE#
REF#
A[17:0]
COD
A[19:18]
BA<2:0>
Table 7 Timing Parameters MRS
COD: Code to be loaded into
the register
Don't Care
Parameter
Mode Register Set cycle time
Symbol
t_MRSC
-3.3
-4.0
-5.0
min max min max min max ^{Units Notes}
4 – 4 – 4 – tCK
Figure 10 Mode Register Bitmap
A<17:7>
A6
A5
A4
A3
Reserved² Test Mode
Driver
Strength
Matched
Mode
Burst
Length
A2
A1
A0
RLDRAM Configuration
A5 Driver Strength¹
0 8mA (default)
1
Do not use
A3 Burst Length
0
2 (default)
1
4
A6
Test Mode
0
(default)
1
test mode
A4 Matched Mode
0 inactive (default)
1
active³
Note: 1 HSTL compliant current specification
Note: 2 Bits A<17:6> must be set to zero
Note: 3 Automatic IO impedance calibration is activated in Matched Mode
A2 A1 A0
000
001
010
011
100
101
110
111
RLDRAM
configuration
3 (default)
1
2
3
4
Do not use
Do not use
Do not use
Version 1.60
Page 16
Infineon Technologies
This specification is preliminary and subject to change without notice