HYB18RL25632AC Datasheet, PDF (11/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1.4 Functional Block Diagram
Figure 4 Functional Block Diagram 8M x 32 Configuration
Column Address
Counter
A0-A18, B0, B1, B2
Column Address Buffer
Row Address Buffer
Row Decoder
Memory Array
Bank 0
Row Decoder
Memory Array
Bank 1
Row Decoder
Memory Array
Bank 2
Refresh Counter
Row Decoder
Memory Array
Bank 3
Row Decoder
Memory Array
Bank 4
Row Decoder
Memory Array
Bank 5
Row Decoder
Memory Array
Bank 6
Row Decoder
Memory Array
Bank 7
Output Data Valid
Data read strobe
DVLD
DQS[3:0], DQS#[3:0]
Input Buffers
Output Buffers
DQ0-DQ31
Note: When the BL4 setting is used, A18 is a "Don’t Care"
Control Logic and Timing Generators
Version 1.60
Page 11
Infineon Technologies
This specification is preliminary and subject to change without notice