HYB18RL25632AC Datasheet, PDF (12/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 5 Functional Block Diagram 16M x 16 Configuration
Column Address
Counter
Row Decoder
Memory Array
Bank 0
A0-A19, B0, B1, B2
Column Address Buffer
Row Address Buffer
Row Decoder
Memory Array
Bank 1
Row Decoder
Memory Array
Bank 2
Refresh Counter
Row Decoder
Memory Array
Bank 3
Row Decoder
Memory Array
Bank 4
Row Decoder
Memory Array
Bank 5
Row Decoder
Memory Array
Bank 6
Row Decoder
Memory Array
Bank 7
Output Data Valid
Data read strobe
DVLD
DQS[1:0], DQS#[1:0]
Input Buffers
Output Buffers
DQ0-DQ15
Note: 1 When the BL4 setting is used, A19 is a "Don’t Care".
Note: 2 In the 16Mx16 configuration, only DQS[1:0] & DQS#[1:0] are used
Control Logic and Timing Generators
Version 1.60
Page 12
Infineon Technologies
This specification is preliminary and subject to change without notice