HYB18RL25632AC Datasheet, PDF (31/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.4.2 x32 Configuration
Scan
Reg#
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
Reg
Content
Data
Enb
Data
Enb
Data
Enb
Data
Enb
Data
Data
Data
Enb
Data
Enb
Data
Enb
Data
Enb
Data
Data
Data
Data
Data
Data
Data
Data
Pin
Descr
.
I/O
I/O
I/O
I/O
O
O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
Pin
Name
DQ1
DQ0
DQ3
DQ2
DQS0#
DQS0
DQ4
DQ5
DQ6
DQ7
DVLD
A1
A2
A0
A3
A4
B0
CK
Ball #
B10
B11
C10
C11
D10
D11
E11
E10
F11
F10
F12
G11
G10
G12
H12
H11
J11
J12
51
Data
I
CK# K12
50
Data
I
B1
K11
49
Data
I
A14 L11
48
Data
I
A13 L12
47
Data
I
A10 M12
46
Data
I
A12 M10
45
Data
I
A11 M11
44
Data
I
A18 N12
43
42
Data
Enb
I/O DQ31 N10
41
40
Data
Enb
I/O DQ30 N11
39
38
Data
Enb
I/O DQ29 P10
37
36
Data
Enb
I/O DQ28 P11
35
Data
O DQS3 R11
34
Data
O DQS3# R10
33
32
Data
Enb
I/O DQ26 T11
31
30
Data
Enb
I/O DQ27 T10
29
28
Data
Enb
I/O DQ24 U11
27
26
Data
Enb
I/O DQ25 U10
Ball #
B3
B2
C3
C2
D3
D2
E2
E3
F2
F3
F1
G2
G3
G1
H1
H2
J2
J1
Pin
Name
Pin
Descr
.
DQ9 I/O
DQ8 I/O
DQ11 I/O
DQ10 I/O
DQS1# O
DQS1 O
DQ12 I/O
DQ13 I/O
DQ14 I/O
DQ15 I/O
DM0
I
A6
I
A7
I
A5
I
A8
I
A9
I
B2
I
AS#
I
Reg
Content
Enb
Data
Enb
Data
Enb
Data
Enb
Data
Data
Data
Enb
Data
Enb
Data
Enb
Data
Enb
Data
Data
Data
Data
Data
Data
Data
Data
Data
Scan
Reg #
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
K1 WE#
I
Data
0
K2 REF# I
Data
1
L2
CS#
I
Data
2
L1
A19
I
Data
3
M1
A15
I
Data
4
M3
A17
I
Data
5
M2
A16
I
Data
6
N1 DM1
I
Data
7
N3 DQ23 I/O
Enb
Data
8
9
N2 DQ22 I/O
Enb
Data
10
11
P3 DQ21 I/O
Enb
Data
12
13
P2 DQ20 I/O
Enb
Data
14
15
R2 DQS2 O
Data
16
R3 DQS2# O
Data
17
T2 DQ18 I/O
Enb
Data
18
19
T3 DQ19 I/O
Enb
Data
20
21
U2 DQ16 I/O
Enb
Data
22
23
U3 DQ17 I/O
Enb
Data
24
25
Note: 1: Input pins are connected to Observe-Only Boundary Scan Register Cells.
Note: 2: Output pins are connected to Force-Only Boundary Scan Register Cells.
Note: 3: IO pins are connected to Control-and-Observe Boundary Scan Register Cells.
Note: 4: For BL 4 the content of the register 101 will be set to 0 if A18 is not connected. Otherwise, the register content will be equal
to the logical value applied to pin A18.
Version 1.60
Page 30
Infineon Technologies
This specification is preliminary and subject to change without notice