HYB18RL25632AC Datasheet, PDF (22/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5.4 Write followed by Read
2.5.4.5 Burst Length (BL) = 2
Figure 17 Write followed by Read BL = 2, RL = 5, WL = 2
0
1
2
3
4
5
6
7
8
9
CK#
CK
Com
WR
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr
A
BA0
A
BA1
A
BA2
WL = 2
RL = 5
DQ
D0a D0b
t_CKDQS
Q1a Q1b Q2a Q2b
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y of bank x
Read Latency
Don't Care
2.5.4.6 Burst Length (BL) = 4
Figure 18 Write followed by Read BL = 4, RL = 5, WL = 1
0
1
2
3
4
5
CK#
CK
Com
WR
RD
NOP
RD
NOP
NOP
Addr
A
A
BA0
BA1
WL = 1
A
BA1
RL = 5
DQ
D0a D0b D0c D0d
6
7
8
9
NOP
NOP
NOP
NOP
t_CKDQS
Q1a Q1b Q1c Q1d Q2a Q2b Q2c
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y of bank x
Read Latency
Don't Care
Version 1.60
Page 21
Infineon Technologies
This specification is preliminary and subject to change without notice