HYB18RL25632AC Datasheet, PDF (20/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5.2 Write - Cyclic Bank Access
2.5.2.1 Burst Length (BL) = 2
Figure 13 Write Burst Basic Sequence, BL = 2, WL = 3
CK#
CK
Com
Add
0
WR
A
BA0
1
2
WR
WR
A
BA1
A
BA2
WL = 3
3
WR
A
BA3
4
WR
A
BA4
5
WR
A
BA5
6
WR
A
BA6
7
WR
A
BA7
8
WR
A
BA0
DQ
D0a D0b D1a D01db D2a D2b D3a D3b D4a D4b D5a
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
Don't Care
2.5.2.2 Burst Length (BL) = 4
Figure 14 Write Burst Basic Sequence, BL = 4, WL = 2
0
1
2
3
4
5
6
7
8
CK#
CK
Com
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
A
A
A
A
A
Addr
BA0
BA1
BA2
BA3
BA0
WL = 2
DQ
D0a D0b D0c D0d D1a D1b D1c D1d D2a D2b D2c D2d D3a
A / BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
Don't Care
Version 1.60
Page 19
Infineon Technologies
This specification is preliminary and subject to change without notice