HYB18RL25632AC Datasheet, PDF (18/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.4 Configuration Table
The following table shows, for different operating frequencies, the different RLDRAM configurations that can
be programmed into the Mode Register. The Read Latency (tRL) and the Write Latency (tWL) used by the
RLDRAM for the two Burst Lengths (BL) are also indicated. Finally the minimum row cycle time (tRC) in clock
cycles and in ns are shown as well. The shaded areas correspond to configurations that are not allowed.
Table 8 RLDRAM configuration table
Configuration
Frequency
Unit
1
2
3
4
300 MHz (-3.3)
250 MHz (-4.0)
200 MHz (-5.0)
tRC
tRL
tWL (BL2)
tWL (BL4)
tRC
tRL
tWL (BL2)
tWL (BL4)
tRC
tRL
tWL _(BL2)
tWL _(BL4)
tRC
tRL
tWL (BL2)
tWL _(BL4)
cycles
cycles
cycles
cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
7
8
5
5
5
6
2
2
2
3
1
1
1
2
26.7
20
10
6.7
28.0
32.0
20.0
24.0
8.0
12.0
4.0
8.0
25.0
30.0
35.0
40.0
25.0
25.0
25.0
30.0
10.0
10.0
10.0
15.0
5.0
5.0
5.0
10.0
Note: 1: The speed sort -3.3 provides parts functional up to 300MHz in the configuration 4 only. The functionality of the configurations
1,2 and 3 is not guaranteed for speed sort -3.3.
Note: 2: The speed sort -4.0 provides parts functional up to 250MHz in the configurations 3 and 4 only. The functionality of the
configurations 1 and 2 is not guaranteed for speed sort -4.0.
Note: 3: The speed sort -5.0 provides parts functional in all configurations.
Version 1.60
Page 17
Infineon Technologies
This specification is preliminary and subject to change without notice