HYB18RL25632AC Datasheet, PDF (33/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.7 JTAG TAP Controller State Diagram
Figure 28 TAP Controller State Diagram
TMS
TCK
Test A ccess P ort (TA P ) C ontroller
0
B ypass R egister
TDI
76543210
Instructio n R egister
31 30
10
ID C od e R eg ister
103
0
TDO
102
1
3.8 JTAG DC Operating Conditons
Parameter
Symbol
Limit Values
Unit Notes
min. typ. max.
Input logic high voltage, VTIH VREF - VDDQ V
DC
+ 0.15
+ 0.3
Input logic low voltage, VTIL VSSQ - VREF V
DC
-0.3
- 0.15
Output logic high
VTOH VREF -
voltage (IOH = -tbd mA)
+ tbd
-
V
Output logic low voltage VTOL
-
(IOL = tbd mA)
- VREF V
- tbd
Version 1.60
Page 32
Infineon Technologies
This specification is preliminary and subject to change without notice