HYB18RL25632AC Datasheet, PDF (32/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.5 TAP Operation
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while
the RLDRAM clock operates much faster. As a consequence, it is possible that an input or output will
undergo a transition right at the moment when the TAP takes the snapshot in the Capture-DR state of the
SAMPLE/PRELOAD instruction. The TAP may then try to capture a signal while in transition (metastable
state). This will not harm the device, but there is no guarantee as to the value that will be captured. To
guarantee that the boundary scan register will capture the correct value of a signal, the signal must meet the
TAP's setup and hold time ( tCS plus tCH) around the rising edge of TCK.
3.6 JTAG TAP Block Diagram
Figure 27 TAP Block Diagram
TMS
TCK
Test Access Port (TAP) Controller
0
Bypass Register
TDI
76543210
Instruction Register
103
31 30
10
ID Code Register
TDO
0
102
1
Version 1.60
Page 31
Infineon Technologies
This specification is preliminary and subject to change without notice