HYB18RL25632AC Datasheet, PDF (24/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Table 10 READ Timing Parameters for -2.5, -3-3 and -5.0 speed sorts
Parameter
Symbol
-3.3
-4.0
-5.0
Units Notes
min max min max min max
Read Cycle Timing Parameters for Data and Data Strobe
DQS / DQS# high pulse width t_DQSH 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS / DQS# low pulse width
t_DQSL 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS edge to Clock edge skew t_CKDQS 2.9 3.9 2.9 3.9 2.9 3.9 ns
DQS edge to output data edge t_QSQ -0.35 0.35 -0.35 0.35 -0.35 0.35 ns
DQS edge to Data Out HiZ
t_QSQHZ
0.4
0.4
0.4 ns
4
DQS edge to DVLD edge
t_QSVLD -0.4 0.4 -0.4 0.4 -0.4 0.4 ns
Note: 1 All timings are measured relatively to the crossing point of CK/CK# (DQSx/DQSx#), and to the crossing point with VREF of
the Command and Address signals.
Note: 2. The signal imput slew rate must be ≥ 1V/ns.
Note: 3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
Note: 4. tDQSQ and tQSQHZ are absolute values.
Version 1.60
Page 23
Infineon Technologies
This specification is preliminary and subject to change without notice