HYB18RL25632AC Datasheet, PDF (23/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.6 Reads (RD)
2.6.1 Read - Basic Information
Read accesses are initiated with a READ command, as shown in
Figure 19. Row and bank addresses are provided with the READ
command.
During READ bursts the memory device drives the read data edge
aligned with the DQS signal. After a programmable read latency, data
is available at the outputs. The data valid signal indicates that valid
read data will be present on the bus after 0.5clock cycles.
The skew between DQS and CK is specified as tCKDQS.
tQSQ is the skew between DQS edge and the last valid data edge.
tQSQ is derived at each DQS clock edge and is not cumulative over
time.
After completion of a burst, assuming no other commands have been
initiated, output data will go High-Z. Back to back READ commands are
possible, producing a continuous flow of output data.
The data valid window is derived for each DQS transition and is defined
as: min(tDQSH, tDQSL) - 2* tQSQmax.
Any READ burst may be followed by a subsequent WRITE command.
Figure 23 shows the corresponding timing requirements for a READ
followed by a WRITE. A READ to WRITE delay has to be buit in in order
to prevent bus contention. Some systems having long line lengths or
severe skews may need additional idle cycles inserted.
Figure 19
READ command
CK#
CK
CS#
AS#
WE#
REF#
A<19:0>
A
BA<2:0>
BA
A:
Address
BA:
Bank Address
Don't Care
Figure 20 Basic Read Burst Timing
CK#
CK
t_CKH
t_CKL
DQS
DQS#
DVLD
t_QSVLD
t_CK
t_CKDQS
t_DQSL
t_DQSH
t_QSVLD
DQ
D0
D1
D2
D3
t_QSQ
t_QSQ
data
valid
window
Don't Care
Version 1.60
Page 22
Infineon Technologies
This specification is preliminary and subject to change without notice