HYB18RL25632AC Datasheet, PDF (35/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
z Storage temperature range............................................– 55 to + 150 ° C
z Input/output pins voltage........................................– 0.3 to VDDQ + 0.3V
z Inputs and VREF voltage.......................................– 0.3 to VDDQ + 0.3V
z Power supply voltage VDD ............................................... – 0.3 to + 2.1V
z Power supply voltage VEXT ................................ ........... – 0.3 to + 2.8V
z Power supply voltage VDDQ ............................................ – 0.3 to + 2.1V
z Junction Temperature......................................................... 0°C to 100°C
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
4.2 Recommended Power & DC Operation Ratings
All values are recommended operating conditions unless otherwise noted.
Table 13 Power & DC Operating Conditions
Parameter
Power Supply Voltages
Power Supply Voltage for I/O
Reference Voltage
Input leakage current
CLK Input leakage current
Output leakage current
VREF Current
Symbol min.
typ.
VEXT
2.38
2.5
VDD
1.75
1.8
VDDQ
1.75
1.85
Vref
0.49*
VDDQ
0.9
II_L
-5
II_LC
-5
I_OL
-5
IREF
-5
max.
2.63
1.85
1.95
0.51*
VDDQ
+5
+5
+5
+5
Unit Notes
V
V
V
V 1,2,3
µA
µA
µA
µA
Matched Impedance 1.8V
Input logic high voltage, DC
Input logic low voltage, DC
Output high voltage
Output low voltage
VI_H
Vref + 0.15
–
VDDQ + 0.3 V
VI_L
VSSQ - 0.3
–
Vref - 0.15 V
VOH
VDDQ
-
-
V
VOL
-
-
0
V
HSTL strong
Input logic high voltage, DC
Input logic low voltage, DC
Output high voltage
Output low voltage
VI_H
Vref + 0.1
–
VDDQ + 0.3 V
VI_L
VSSQ - 0.3
–
Vref - 0.1 V
VOH VDDQ-0.4
-
-
V
VOL
-
-
0.4
V
Note: 1. Typically the value of Vref is expected to be 0.5 * VDDQ of the transmitting device. Vref is expected to track variations in VDDQ
Note: 2. Peak to peak AC noise on Vref may not exceed 2% Vref (DC)
Note: 3. Vtt of the transmitting device must track Vref of the receiving device.
Note: 4. Recommanded on board decouping capacitors : VDDQ: 2 x 0.1µF / device, VDD: 2 x 0.1µF / device, VREF : 0.1µF / device,
VEXT: 0.1µF / device.
Version 1.60
Page 34
Infineon Technologies
This specification is preliminary and subject to change without notice