HYB18RL25632AC Datasheet, PDF (25/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.6.2 Read - Cyclic Bank Access
2.6.2.1 Burst Length (BL) = 2
Figure 21 Read Burst, BL = 2, RL = 5
0
1
2
3
4
CK#
CK
Com.
RD
RD
RD
RD
RD
Addr.
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
DQS
DQS#
DQ
RL = 5
2.6.2.2 Burst Length (BL) = 4
Figure 22 Read Burst, BL = 4, RL = 5
0
1
2
3
4
CK#
CK
Com.
RD
NOP
RD
NOP
RD
Addr.
A
BA0
A
BA1
A
BA2
DQS
DQS#
DQ
RL = 5
5
6
7
8
RD
A
BA5
RD
RD
A
A
BA6
BA7
t_CKDQS
RD
A
BA0
Q0a Q0b Q1a Q1b Q2a Q2b Q3a
A / BAx:
RD:
Qxy:
RL:
address A of bank x
READ
Data part y from bank x
Read Latency
Don't Care
5
6
7
8
NOP
RD
NOP
A
BA3
t_CKDQS
RD
A
BA0
Q0a Q0b Q0c Q0d Q1a Q1b Q1c
A / BAx:
RD:
Qxy:
RL:
address A of bank x
READ
Data part y from bank x
Read Latency
Don't Care
Version 1.60
Page 24
Infineon Technologies
This specification is preliminary and subject to change without notice