HYB18RL25632AC Datasheet, PDF (29/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
3.2.3 Boundary Scan Register
The boundary scan register is connected to all the IO pins on the RLDRAM. It allows to observe and control
the data flowing into and out of the device, depending on the instruction being loaded in the instruction
register.
The boundary scan register is 104 bits long. The register is the same for the x16 and x32 configurations of
the RLDRAM. Pins not used in the x16 configurations read a HIGH into the boundary scan register in the
Capture-DR controller state.
Differential inputs (CK/CK#) and outputs (DQSx/DQSx#) are equipped with two boundary scan cells each.
Thus, the differential nature of these pins is not visible to the test circuitry. However, it is recommended that
during testing differential signals are always applied to these pin pairs.
3.2.4 Identification (ID) Register
The ID register is loaded with a hardwired, vendor-specific, 32-bit code during the Capture-DR state when
the IDCODE instruction is loaded in the instruction register. The code can be shifted out when the TAP
controller is in the Shift-DR state. Two different codes are implemented for the x16 and x32 configurations
of the RLDRAM (see Table 11).
.
Table 11 ID Register Definition
Revision
Part Number
Infineon JEDEC Code L
Number
S
B
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x16 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1
x32 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1
3.3 TAP Instructions
The TAP implements the 6 instructions BYPASS, EXTEST, SAMPLE/PRELOAD and IDCODE for user
access (see Table 12). The implementation of these instructions fully complies with the IEEE standard. All
other instructions are reserved and should not be used.
Table 12 JTAG Instruction Register
Instruction Register
Code
Hex
x7 .. x0
00 0000 0000
05 0000 0101
21 0010 0001
FF 1111 1111
Instruction
Description
EXTEST
Selects the boundary scan register to be connected between TDI
and TDO. Data received at input pins are sampled and loaded into
the boundary scan register. Data driven by output pins are
determined from values contained in the boundary scan register.
SAMPLE / PRELOAD
Selects the boundary scan register to be connected between TDI
and TDO. Data receivedat input pins are sampled and loaded int the
boundary scan register. initial ouput data are shifted into the
boundary scan register prior to an EXTEST intruction. Instruction
does not interfere with the normal operation of the device.
IDCODE
Selects the ID code register to be connected to TDI and TDO.
Instructin does not interfere with the normal operation of the device.
BYPASS
Selects the bypass register to be connected between TDI and TDO.
Instruction does not interfere with the normal operation of the
device.
Version 1.60
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Infineon Technologies
This specification is preliminary and subject to change without notice