HYB18RL25632AC Datasheet, PDF (19/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5 Writes (WR)
2.5.1 Write - Basic Information
Write accesses are initiated with a WRITE command, as shown in
Figure 11. Row and bank addresses are provided together with the
WRITE command.
During WRITE commands, data will be registered at both edges of CK
according to the programmed burst length BL. The first valid data is
registered with the first rising CK edge WL (Write Latency) cycles after
the WRITE command has been issued.
Any WRITE burst may be followed by a subsequent READ command.
Figure 17 and Figure 18 illustrate the timing requirements for a WRITE
followed by a READ for a burst of 2 and 4 respectively.
Setup and hold time for incoming DQs relative to the CK edges are
specified as tDS and tDH.
The first or the second part of the incoming data burst is masked if the
corresponding DMx signal is sampled HIGH along with the WRITE
command. Setup and hold time for DM is the same as for addresses
and commands.
Figure 11
Write command
CK#
CK
CS#
AS#
WE#
REF#
DM[1:0]
DM
A[19:0]
A
BA[2:0]
BA
Figure 12 Basic Write Burst Timing
A:
BA:
DM:
Address
Bank Address
Data Mask
Don't Care
CK#
CK
Write Latency
DQ
t_DS t_DH
D0
D1
t_DS t_DH
D2
D3
Don't Care
Table 9 WRITE Timing Parameters
Parameter
Data-in to CK Setup Time
Data-in to CK Hold Time
Symbol
t_DS
t_DH
-3.3
min max
0.5 –
0.5 –
-4.0
min max
0.5 –
0.5 –
-5.0
min max ^{Units Notes}
0.5 –
ns
0.5 –
ns
Note: 1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and
Address signals.
Note: 2. The signal imput slew rate must be ≥ 1V/ns.
Note: 3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
Version 1.60
Page 18
Infineon Technologies
This specification is preliminary and subject to change without notice