HYB18RL25632AC Datasheet, PDF (27/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Figure 25 Read followed by Write, BL=4, RL = 5, WL = 1
0
1
2
3
4
5
6
7
8
9
10
CK#
CK
Com.
RD
NOP
NOP
NOP
NOP
NOP
NOP
WR
NOP
NOP
NOP
Addr.
A
BA0
A
BA1
RL = 5
t_CKDQS
WL = 1
DQ
Q0a Q0b Q0c Q0d
D1a D1b D1c D1d
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Don't Care
Figure 26 Read followed by Write, write data on system bus prior read data, BL=4, RL=5, WL=1
0
CK#
CK
Com.
RD
1
2
3
4
5
6
7
8
WR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr.
A
BA0
A
BA1
WL = 1
RL = 5
DQ
D1a D1b D1c D1d
t_CKDQS
Q0a Q0b Q0c Q0d
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Don't Care
Version 1.60
Page 26
Infineon Technologies
This specification is preliminary and subject to change without notice