HYB18RL25632AC Datasheet, PDF (36/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
4.3 AC Operation Ratings
Table 14 AC Operation Conditions for Matched Impedance mode
Parameter
Symbol
min.
typ.
max. Unit Notes
Matched Impedance 1.8V
Input logic high voltage, AC DDR
VI_H Vref + 0.3
– VDDQ + 0.3 V
Input logic low voltage, AC DDR
VI_L VSSQ - 0.3 –
Vref - 0.3 V
Clock Differential Input Voltage (CLK/ CLK#) VI_D
0.6
– VDDQ + 0.6 V
Clock Input Crossing Point (CLK/ CLK#)
VI_X Vref - 0.15 Vref Vref + 0.15 V
I/O Reference Voltage
Vref 0.49*VDDQ
0.51*VDDQ V
HSTL strong
Input logic high voltage, AC DDR
VI_H Vref + 0.3
– VDDQ + 0.3 V
Input logic low voltage, AC DDR
VI_L VSSQ - 0.3 –
Vref - 0.3 V
Clock Differential Input Voltage (CLK/ CLK#) VI_D
0.6
– VDDQ + 0.6 V
Clock Input Crossing Point (CLK/ CLK#)
VI_X Vref - 0.15 Vref Vref + 0.15 V
I/O Reference Voltage
Vref 0.49*VDDQ
0.51*VDDQ V
4.4 Output Test Conditions
Figure 29 Output Test Circuits
+ V_tt = 0.5 x V_DDQ
50 Ohm
DQ
Test point
20 pF
DQ
Test point
10 pF
HSTL
Matched Impedance Mode
Note: VDDQ=1.8V ±0.1V, TJ = 0 ° C to 100 ° C
4.5 Pin Capacitances
Table 15 Pin Capacitances
Pin
A<19:0>, BA<2:0>, CS#, AREF#, WE#
CLK, CLK#
DQ<31:0>, DQS0, DQS0#, DQS1, DQS1#, DVLD, DM
Min
Typ.
Max
Unit
2.0
3.0
4.0
pF
2.0
3.0
4.0
pF
2.0
3.0
4.0
pF
Version 1.60
Page 35
Infineon Technologies
This specification is preliminary and subject to change without notice