HYB18RL25632AC Datasheet, PDF (15/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2 Functional Description
2.1 Clocks, Commands and Addresses
Figure 6 Clock Command/Address Timings
CK#
CK
CMD,
ADDR
t_CK
t_CKH
t_CKL
Vaild
Vaild
Vaild
t_AS, t_CS t_AH, t_CH
Don't Care
Table 6 General Timing Parameters for -2.5, -3.3 and -5.0 ns speed sorts
Parameter
Symbol
Clock
Clock Cycle Time
t_CK
Clock high level width
tCKH
Clock low level width
tCKL
Setup Times
Address/Command input setup time t_AS, t_CS
Hold Times
Address/Command input hold time t_AH, t_CH
-3.3
min max
3.3
-
0.45 0.55
0.45 0.55
1.0
–
1.0
–
-4.0
min max
4.0
-
0.45 0.55
0.45 0.55
1.0
–
1.0
–
-5.0
Units
min max
5.0
-
ns
0.45 0.55 tCK
0.45 0.55 tCK
1.0
–
ns
1.0
–
ns
Note: 1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and
Address signals.
Note: 2. The signal imput slew rate must be ≥ 1V/ns.
Note: 3. CK/CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
Version 1.60
Page 14
Infineon Technologies
This specification is preliminary and subject to change without notice