HYB18RL25632AC Datasheet, PDF (5/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
1 Overview
1.1 Features
z 256 Megabit (256M)
z 0.17µm process technology
z Cyclic bank addressing for maximum data out bandwidth
z Organization 8M x 32, 16M x 16 in 8 banks
z Non-multiplexed addresses
z Non-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), DDR
z Up to 600Mb/sec/pin data rate
z Programmable Read Latency (RL) of 5..6
z Data valid signal (DVLD) activated as Read Data is available
z Data Mask signals (DM0 / DM1) to mask first and second part of write data burst
z IEEE 1149.1 compliant JTAG Boundary Scan
z Pseudo-HSTL 1.8V IO Supply
z Internal autoprecharge
z Refresh requirements: 32ms at 100°C junction temperature (8k refresh for each bank, 64k refresh
commands must be issued in total each 32ms)
z Package T-FBGA 144
z 2.5V VEXT, 1.8V VDD, 1.8V VDDQ
Table 1 Key timing parameters (Configuration Example x32, x16 device)
Speed Sort
-3.3
-4.0
-5.0
Units
Frequency
300
250
200
MHz
26.7
28.0
25.0
ns
tRC
8
7
5
cycles
Read latency
6
5
5
cyles
Version 1.60
Page 5
Infineon Technologies
This specification is preliminary and subject to change without notice