HYB18RL25632AC Datasheet, PDF (26/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.6.3 Read followed by Write
Figure 23 Read followed by Write, BL=2, RL = 5, WL = 2
0
1
2
3
4
5
6
CK#
CK
Com.
RD
NOP
NOP
NOP
NOP
WR
WR
Addr.
A
BA0
DQ
RL = 5
A
A
BA1
BA2
WL = 2
t_CKDQS
Q0a Q0b
7
8
NOP
NOP
D1a D1b D2a D2b
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Don't Care
Figure 24 Read followed by Write, Write data on bus prior Read data, BL=2, RL=5, WL=2
0
1
2
3
4
5
6
7
8
CK#
CK
Com.
RD
WR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Addr.
A
BA0
A
BA1
WL = 2
RL = 5
DQ
D1a D1b
t_CKDQS
Q0a Q0b
DQS
DQS#
A/BAx:
WR:
Dxy:
WL:
address A of bank x
WRITE
Data part y to bank x
Write Latency
RD:
Qxy:
RL:
READ
Data part y from bank x
Read Latency
Don't Care
Version 1.60
Page 25
Infineon Technologies
This specification is preliminary and subject to change without notice